Digital Logic Syllabus

Course Code: BCA114

Course Title: Digital Logic (4 Credits)




Course Contents


Unit 1 Number Systems: Introduction to Number Systems: The Decimal Number System: The Binary Numbering System; Counting in Binary, Binary to Decimal Conversion, Decimal to Binary Conversion,  Sum of Weight Method, Repeated Division Method, Repeated Multiplication: The Octal Numbering System; Counting in Octal, Octal to Decimal Conversion, Decimal to Octal Conversion, Sum of Weight Method, Repeated Division Method, Repeated Multiplication, Octal to Binary Conversion, Binary to Octal Conversion: The Hexadecimal Numbering System; Hexadecimal to Binary Conversion, Binary to Hexadecimal Conversion, Hexadecimal to Decimal Conversion, Hexadecimal to Octal Conversion, Decimal to Octal Conversion, Sum of Weight Method, Repeated Division Method, Repeated Multiplication: Binary Arithmetic; Binary Addition, Binary Subtraction, Binary Multiplication, Binary Division, Complementary numbering systems: 1’s and 2’s Complements, Binary subtraction using 1’s complementary Method, Binary subtraction using 2’s complementary Method: Binary Coded Decimal (BCD) Numbering system, BCD Addition:


Unit 2 Boolean Algebra: Introduction to Boolean Algebra: Addition and Multiplication in Boolean algebra: Binary Logic Functions, Logical Gates and Truth Tables; NOT Logic, AND Logic, OR Logic, NAND Logic, NOR Logic, Ex – OR Logic, Ex – NOR Logic: Boolean Rules and Laws; Commutative law, Associative Law, Distributive Law, Boolean Rules: DEMORGAN’s Theorem:


Unit 3 Combinational Logic: Introduction: Realization of switching functions using logic gates: Canonical Logic Forms; Sum of Products Form, Product of Sum Form: Universal Gate; NAND Gate as Universal Gate, NOR Gate as Universal Gate, Realization of Boolean Functions using Universal Gates: Timing Diagrams and Synchronous Logic: Realization of Combinational circuits from the truth table:


Unit 4 Combination logic realization: Introduction: Karnaugh Map or K – Map: Plotting a Boolean expression: Logic expression simplification with grouping cells: Quine McClusky Method; Prime implicants, Prime implicant chart: Multiple Output functions:


Unit 5 Analysis and Design of Combinational Logic: Introduction: Binary adders; Half adder, Full adder: Binary Subtractor; Half subtractor, Full subtractor: Parallel Binary Adders: BCD Adders: Binary Comparator or Magnitude Comparator: Decoders; Basic Binary Decoder, 3 line to 8 line Decoder: Encoders; Decimal to BCD encoder, Octal to Binary Encoder: Priority Encoder; Decimal to BCD priority encoder: Code conversion; BCD to Binary conversion, Gray Code, Binary to Gray Conversion: , Gray code to Binary Conversion: Multiplexers or Data Selectors: Multiplexers as logic function generators: Demultiplexers: Parity Generators and Parity Checkers; Parity, Detecting an Error:


Unit 6 Latches and Flip Flops: Introduction: Latches: The S-R Latch; Active HIGH S-R Latch (NOR gate S-R Latch), Active Low  S-R Latch ( NAND Gate S-R Latch): Gated Latches; Gated S-R Latches, Gated D-Latch or D-flip-flop: Edge triggered Flip-Flops; Edge triggered S-R Flip-Flop (S-R FF), Edge triggered D-Flip-Flop (D-FF), Edge triggered J-K Flip-Flop (J-K FF): Asynchronous inputs: PRESET and CLEAR: Master-Slave J-K Flip Flop:


Unit 7 Asynchronous Counters: Introduction: Asynchronous Counters; Negative edge triggered 2-bit ripple Up-counter, Negative edge triggered 2-bit ripple Down-counter, Negative edge triggered 2-bit ripple up/down-counter: Design of modulus counters: Cascading of Ripple Counter: Integrated Circuit Asynchronous Ripple Counter; IC 7493 – A 4-bit Binary Counter, IC 7490 – A Decade Counter:


Unit 8 Synchronous Counters: Introduction: Up- Counters;       Two bit Synchronous Binary Counters, A Three-bit Synchronous Binary Up-counter, A Four-bit Synchronous Binary Up-counter, Synchronous Decade Up-counter: Down- Counters; Two bit Synchronous Binary Counters, A Three-bit Synchronous Binary down-counter, A Four-bit Synchronous Binary down-counter: Synchronous Up-down counters:


Unit 9 Shift Registers: Introduction: Shift Register Classification: Serial-in, Serial-out shift register; Timings in Serial Shift operation, Serial In, Serial out Shift operation – 3 register combination: Serial In, Parallel out Shift Register: Parallel In, Parallel out Shift Register: 74LS395 – A Universal Shift Register; Serial in, Serial Out Right Shift Operation of 74LS395, Serial in, Serial Out Left Shift Operation of 74LS395: Ring counters: Johnson counters:


Unit 10 Data Converters: Introduction: Digital to Analog Converters (DAC); Binary Weighted Input Method, The R-2R Ladder DAC: Analog to Digital Converters (ADC); Flash Type ADC, Staircase Ramp or Digital Ramp Type, Slope Integrator Type, Single Slope Integrator Type, Dual Slope Integrator Type, Successive Approximation Method: Practical Considerations of ADCs; Resolution, Conversion Rate or Sample Frequency, Step Recovery: Comparison of ADC Circuitry